Introduction to Verilog Design |
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Training Description:
The Verilog Design trainingprovides a hands-on introduction to Verilog as a hardware description language (HDL) used to model electronic systems. Verilog is most commonly used in the design, verification, and implementation of digital logic chips at the Register transfer level (RTL) level of abstraction. In this introductory training course, you'll gain the expertise you need to write efficient, re-usable RTL code, and create test benches powerful enough to cope with complex designs. The training course will include the following topics:
The Verilog Design trainingprovides a hands-on introduction to Verilog as a hardware description language (HDL) used to model electronic systems. Verilog is most commonly used in the design, verification, and implementation of digital logic chips at the Register transfer level (RTL) level of abstraction. In this introductory training course, you'll gain the expertise you need to write efficient, re-usable RTL code, and create test benches powerful enough to cope with complex designs. The training course will include the following topics:
- Modeling concepts.
- Levels of abstraction.
- Design methodologies. - Basic concepts
- Module, module header format.
- Lexical conventions: comments, identifiers, numbers, strings.
- Data types: nets, registers, vectors, arrays.
- Parameter types. Operators.
- Operator types, precedence.
- Sequential and parallel blocks. Comparison of sequential and parallel blocks.
- Basic compiler directives.
- Behavioral modeling.
- Behavioral modeling blocks: always block, event-based timing control, branch statements, case, casex, casez.
- Procedural assignments: blocking and non-blocking. - Data flow modeling.
- Assign statements.
- Delays. Implicit net declaration.
- Regular, implicit continuous assignment and net declaration delay. Logic statement implementation. The conditional operator. - Gate level modeling.
- Gate types: and/or, buf/not gates, bufif/notif gates.
- Gate truth tables.
- Gate delays. Specify block. UDP. Ports. Port connection rules: by order and name. - Switch level modeling.
- Primitives.
- Use of trireg. - Testbench creation.
- Initial block.
- Delay-based timing control.
- System tasks.
- Monitoring a simulation.
- Looping constructs: while loop, for loop, repeat, forever loop.
- Tasks and functions.
-Differences between tasks and functions.
- VCS simulation examples