IC Design Workshop |
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Course Description:
This course takes participants through an intro to IC Design. Students will be introduced to the basics of IC Design. Fabrication processes and layout design techniques will also be introduced. They will then go through the Digital IC design flow covering the design flows and tools required to successfully implement modern Digital IC designs, ready for manufacture. The course starts with building RTL code, and then examines; synthesis , timing constraints, physical implementation (floorplanning, placement, CTS and routing). Participants will also get introduced to Digital verification techniques. IO design and packaging techniques will be discussed to let the participants understand another important IC design pillar.
All instructors and mentors and experienced industry professionals with multiple years of experience. Participants will meet their instructors 2-3 hours per week to go through the newly discussed material, get hands-on tasks to be performed and discuss what they did in the previous week. They will then work on their hands-on tasks during the rest of the week. Meetings will be mainly Sundays @ 1pm in ASU iHub.
Course Details
Training Class Size:
25 (max)
This course takes participants through an intro to IC Design. Students will be introduced to the basics of IC Design. Fabrication processes and layout design techniques will also be introduced. They will then go through the Digital IC design flow covering the design flows and tools required to successfully implement modern Digital IC designs, ready for manufacture. The course starts with building RTL code, and then examines; synthesis , timing constraints, physical implementation (floorplanning, placement, CTS and routing). Participants will also get introduced to Digital verification techniques. IO design and packaging techniques will be discussed to let the participants understand another important IC design pillar.
All instructors and mentors and experienced industry professionals with multiple years of experience. Participants will meet their instructors 2-3 hours per week to go through the newly discussed material, get hands-on tasks to be performed and discuss what they did in the previous week. They will then work on their hands-on tasks during the rest of the week. Meetings will be mainly Sundays @ 1pm in ASU iHub.
Course Details
- Introduction to the RTL design (25/7/2017)
Eng. Amr Elhosseny
This session will go through the digital design flow. It will cover what is RTL, coding guidelines, and finally it will go through the synthesis - Introduction to digital APR flow (30/7/17)
Eng. Mahmoud Elgazzar
This session will go through the APR flow. It will cover placement, CTS, timing analysis and finally solving the timing violations - Introduction to analog design flow (6/8/17)
Eng. Moamen Mansour
This session will go through the analog design flow. It will show the different steps of designing analog circuit (Building schematic, building TB, corners simulations, MC simulations, PEX simulations, ….). - Introduction to the fabrication process (13/8/17)
Eng. Fady Atef
This session will go through the fabrication process from silicon till we have chip ready for testing. - Introduction to the custom layout flow of chips (20/8/17)
Eng. Fady Atef
This session will go through the custom layout flow. It will cover floor planning, analog layout rules, backend verification (DRC, LVS, ANT, …) - Introduction to the digital verification (27/8/17)
Eng. Ahmed Adel
This session will go through the digital verification flow. It will cover the added gain of the functional verification and show different methodologies for the digital functional verification. - IO ring, bonding & packaging (10/9/17)
Eng. Amr Ahmed
This session will cover interfacing the chip to the external world.
Training Class Size:
25 (max)
