Digital IC Design Workshop :
​From Spec to FPGA

The course spans more than 24 hours over 3 days.
The workshop will be on 27/01,28/01,& 30/01/2018.
​At ​9:30 AM – 5:30 PM.
Location: Room 931, CHEP building, and Mechatronics lab , Toshka building ; Faculty of Engineering, Ain Shams University.
CHEP Training Credit: 1 weeks of Training
Cost: 450 EGP
​

Instructor

Dr Ahmed Shalaby 

Industry Partner

Workshop Description:
This workshop intends to develop student skills and ability to design, model, simulate, and synthesize a real hardware system using Verilog.  Through studying techniques and processes of digital systems design.The workshop will cover:

• Introduction to digital system.
• Introduction to Verilog HDL.
• Structure and Modules.
• Numbers, Wires and Regs.
• Operators, Parameters, Hierarchy
• Combinational modeling.
• Sequential modeling.
• Synthesis basics.

Course Objectives

• Practice extracting system specifications from informal descriptions.
• Model a substantial system given its verbal specification.
• Practice modeling sequential logic using Verilog.
• Exercise sequential logic simulation.
• Write Verilog code that models an FSM.
• Get more experience with Verilog hierarchical design.
• Get in-depth experience with proposing a test strategy and writing a Verilog testbench that realizes it.
• Use the Verilog reference sheets while writing a code.

    
Requirements

• Prior knowledge in Digital Design
• Prior knowledge in Basic Electronic Circuit Design

Equipment and Tools

• FPGA boardsin iHub Labs

Training Class Size: 
20 (max)