Digital IC Design |
Instructor
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Registration Status
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Industry Partner
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Course Description:
This course takes participants through a full state of the art Digital IC implementation flow, covering the design flows and tools required to successfully implement modern Digital IC designs, ready for manufacture. The course starts with building RTL code, and then examines; synthesis , timing constraints, physical implementation (floorplanning, placement, CTS and routing).
Theory and concepts are covered in lectures with significant time given to detailed hands-on practical exercises using the Synopsys digital implementation tools. The design flow is illustrated with an RTL SoC example design (tiny mocroprocessor) which is then taken through to layout (GDSII suitable for manufacture) in a 130nm CMOS process.
Course Details
Training Class Size:
20 (max)
This course takes participants through a full state of the art Digital IC implementation flow, covering the design flows and tools required to successfully implement modern Digital IC designs, ready for manufacture. The course starts with building RTL code, and then examines; synthesis , timing constraints, physical implementation (floorplanning, placement, CTS and routing).
Theory and concepts are covered in lectures with significant time given to detailed hands-on practical exercises using the Synopsys digital implementation tools. The design flow is illustrated with an RTL SoC example design (tiny mocroprocessor) which is then taken through to layout (GDSII suitable for manufacture) in a 130nm CMOS process.
Course Details
- Digital Logic Design (revisit):
- Analog Vs. Digital.
- Basic Gates and Components (Primitive Cells).
- Combinational and Sequential Logic Design.
- Synchronous Circuits Vs. Asynchronous Circuits.
- Edge-Sensitive Vs. Level-Sensitive Components (Flip-flop Vs. Latch).
- Lab: Structural/Behavioral Verilog Coding and Simulation for Basic Components: Full Adder Project!
- Timing Constraints:
- Propagation Delay (Long Paths and Short Paths).
- Setup Time, Hold time, and Clock Skew.
- Determine Critical path.
- Static Timing Analysis.
- Technology Files and Standard Cells Library.
- Lab: Synthesis and Post-Synthesis Simulation for the Full Adder using Synopsys Design Vision!
- Micro-Processor Architecture:
- Pipelining.
- PC Counter.
- ALU.
- Register Files.
- Memory.
- Lab: Verilog Coding and Synthesis for the Micro-processor.
- Physical Design:
- Floor Planning.
- Placement.
- Routing.
- Clock Tree.
- Power Grid.
- I/Os.
- Metal Layers.
- Lab: Place and Route for the Full Adder/Micro-Processor using Synopsys IC Compiler!
Training Class Size:
20 (max)