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Digital IC Design

Instructor
Registration Status
Industry Partner
[Back to the iAcademy Technology Track]
The course spans more than 32 hours over 8 days (2 days/week - Tuesdays/Sundays) starting 25/08/2015
Cost: 400 EGP (Payment needs to be made in ASU by 23/8/2015)

Open
Picture
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Course Description:
This course takes participants through a full state of the art Digital IC implementation flow, covering the design flows and tools required to successfully implement modern Digital IC designs, ready for manufacture. The course starts with building RTL code, and then examines; synthesis , timing constraints, physical implementation (floorplanning, placement, CTS and routing). 

Theory and concepts are covered in lectures with significant time given to detailed hands-on practical exercises using the Synopsys digital implementation tools. The design flow is illustrated with an RTL SoC example design (tiny mocroprocessor) which is then taken through to layout (GDSII suitable for manufacture) in a 130nm CMOS process.

Course Details
  • Digital Logic Design (revisit):
  1. Analog Vs. Digital.
  2. Basic Gates and Components (Primitive Cells).
  3. Combinational and Sequential Logic Design.
  4. Synchronous Circuits Vs. Asynchronous Circuits.
  5. Edge-Sensitive Vs. Level-Sensitive Components (Flip-flop Vs. Latch).
  6. Lab: Structural/Behavioral Verilog Coding and Simulation for Basic Components: Full Adder Project!

  • Timing Constraints:
  1. Propagation Delay (Long Paths and Short Paths).
  2. Setup Time, Hold time, and Clock Skew.
  3. Determine Critical path.
  4. Static Timing Analysis.
  5. Technology Files and Standard Cells Library.
  6. Lab: Synthesis and Post-Synthesis Simulation for the Full Adder using Synopsys Design Vision!

  • Micro-Processor Architecture:
  1. Pipelining.
  2. PC Counter.
  3. ALU.
  4. Register Files.
  5. Memory.
  6. Lab: Verilog Coding and Synthesis for the Micro-processor.

  • Physical Design:
  1. Floor Planning.
  2. Placement.
  3. Routing.
  4. Clock Tree.
  5. Power Grid.
  6. I/Os.
  7. Metal Layers.
  8. Lab: Place and Route for the Full Adder/Micro-Processor using Synopsys IC Compiler!

Training Class Size: 
20 (max)
Copyright © Innovation Hub ( iHub )  2013

  • Home
  • General info
  • ECDC
  • CNC workshop feedback
    • PLC workshop feedback
    • Formula academy
  • Coworking Space
    • iAcademy >
      • iAcademy17
      • iAcademy_Survey >
        • iClubs >
          • iClubs 2020 Registration
      • iAcademy Personal Development Track
  • Programs
    • Entrepreneurship >
      • iSpark 2020 - Wave 1
      • Seminars >
        • Seminar Registeration Form
        • Seminars Feedback
        • Seminar Material
      • iCamp
    • iGP >
      • iGP2021
      • Apply
    • ZEH >
      • 17zeh-submission-form
      • 17ZEH_technical_support_form
    • iLab16
    • internships
    • EVER
  • Calendar
  • About
    • Media
  • CIB Internship
  • Front End Web Development 2021
  • NAID assistive technologies summer internship
  • iCamp Mobile Development
  • iCamp Web Development
  • NAID assistive technologies summer internship-2nd form
  • Category
  • ASU Innovates Researchers - Semi-Finals
  • Researchers'23 Interviews
  • ​​Researchers Interviews 2
  • ASU Innovates Researchers - Bootcamp