Digital IC Design - VERILOG Training

The course spans more than 48 hours over 4 Weeks .
Time:  Starts around Mid of July 2019
Location: iHub Faculty of Engineering, ASU
CHEP Training Credit: 4 weeks
Cost:  2 Credit Hours
​

​Instructor

Dr. Awny M. El-Mohandes 
​Course schedule :-
  • 6 hours / 8 Days. 10:00 AM – 4:00 PM.   
  • 18 hours lectures. Three days.   
  • 12 hours Labs / Mini-Projects. Two days. 
  • 18-hour Final Project. Three days

​  Course Purpose :- 
In this training, we study techniques and processes for digital systems design.
​This training is intended to develop student skills and ability to design, model, simulate, and synthesize a real hardware system using Verilog.

In points, in this training the student should learn how to:
  • Practice extracting system specifications from informal descriptions.
  • Model a substantial system given its verbal specification.
  • Practice modeling combinational and sequential logics using Verilog.
  • Exercise combinational and sequential logics simulation.
  • Write Verilog code that models an FSM.
  • Get more experience with Verilog hierarchical design (structural and behavior).
  • Get in-depth experience with proposing a test strategy and writing a Verilog testbench that realizes it.

​ Topics Covered:In this training we will try to cover the following items:
  • Introduction to digital system.
  • Introduction to Verilog HDL.
  • Structure and Modules.
  • Numbers, Wires and Regs.
  • Operators, Parameters, Hierarchy
  • Combinational modeling.
  • Sequential modeling.
  • Synthesis basics.
  • Project designing, synthesizing, and implementation on FPGA.