Introduction to Verilog Design

Instructor

Industry Partner

Registration Status

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The course spans more than 18 hours over 3 days: 14,16,20/09/2015 using Synopsys tools
Location: iHub Simulation Lab, Room 218, Main Building, Faculty of Engineering, ASU
Cost: 200 EGP 
(Payment needs to be made in ASU by 12/9/2015)

Eng. Fady Atef

Register Below

Training Description:
The Physical IC Design course provides a hands-on training that  will include the following topics:


• CMOS logic processes
• Layout interconnect principles and techniques
1. Floorplanning
2. Connection Techniques
3. Parasitic insertion
• Physical Verification Methodologies
1. Design Rule Checks DRC
2. Layout vs. Schematic LVS
3. Parasitic extraction PEX
4. Electrical rule checks ERC
• Advanced Topics
1. Electrostatic Discharge (ESD) protection
   
2. Antenna
3. Latch Up
4. Soft ERC connections
5. DFM design for manufacturability
6. Electro-migration
• Brief P&R flow
• Tape-out preparations